1. Technical Field
The present invention relates generally to semiconductor memory devices and, more specifically, to a flash memory device and a page buffer circuit of the flash memory device.
2. Description of Related Art
Semiconductor memory devices can be typically categorized into two types: volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while being capable of achieving high-speed read and write operations. Non-volatile memory devices retain their stored data even when their power supplies are interrupted. Thus, non-volatile memory devices are widely used to store data which should be retained irrespective of whether their power supplies are interrupted. Non-volatile memory devices include, for example, mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs).
In MROM, PROM, and EPROM devices, it is inconvenient to erase and write data and, therefore, it is generally difficult to update the contents stored therein. On the other hand, data stored in EEPROM devices can be electrically programmed and erased and, therefore, the use of EEPROM devices is increasingly becoming popular in auxiliary memory devices and system programming devices that require continuous updating of contents. In particular, flash memory devices are advantageously applied to large-capacity auxiliary memory devices because they provide higher integration density than conventional EEPROM devices.
A flash memory device is an integrated circuit which is capable of storing and reading data at any time. A flash memory device includes a plurality of reprogrammable memory cells each storing 1-bit data or multi-bit data therein. When 1-bit data is stored in one memory cell, the memory cell program states correspond to two threshold voltage distributions. That is, the memory cell is programmed to have a threshold voltage corresponding to either one of data “1” and data “0”. A multi-level cell (MLC) including a plurality of memory cells configured to store multi-bit data therein has more program states. Namely, when 2-bit data is stored in one memory cell, the memory cell is programmed to a threshold voltage included in four threshold voltage distributions. When 3-bit data is stored in one memory cell, the memory cell is programmed to a threshold voltage included in eight threshold voltage distributions. Recently, various attempts have been made to store 4-bit data in one memory cell.